Computer Architecture 1R
Data is displayed for the academic year: 2024./2025.
Lectures
Laboratory exercises
Course Description
This course gives basic understanding of processor architecture and computer system organization. Principles are explained using simple RISC processor and commercial ARM CPU architecture. Internal architecture of a processor is explained together with the details of the instruction execution. Assembly language programming is explained. Interfacing with memory and IO units is explained.
Prerequisites
Digital logic
Study Programmes
University undergraduate
[FER3-EN] Computing - study
(3. semester)
Learning Outcomes
- list the main parts of processors and computers
- explain how processors execute instructions
- explain the function of the main parts of a processor
- solve simple programming problems in assembly language
- explain the interfacing and communication between processor, memoy, and IO units
- solve simple problems of communication between processor and IO units
Forms of Teaching
Lectures
Lectures are held every week (4 hours per week). Theoretical foundations of computer architecture are explained together with practical programming examples using assembly language.
Independent assignmentsStudents solve simple problems using assembly language programming.
LaboratoryStudents write, debugg and execute assembly programs by using a computer architecture simulator.
Grading Method
Continuous Assessment | Exam | |||||
---|---|---|---|---|---|---|
Type | Threshold | Percent of Grade | Threshold | Percent of Grade | ||
Laboratory Exercises | 20 % | 15 % | 20 % | 15 % | ||
Mid Term Exam: Written | 0 % | 40 % | 0 % | |||
Final Exam: Written | 0 % | 45 % | ||||
Exam: Written | 0 % | 85 % |
Comment:
All Laboratory excercises must be succesfully completed (you dont get points for that) in order to get the passing grade.
Week by Week Schedule
- Overview and history of computer architecture, Multiple representations/layers of interpretation (hardware is just another layer), Bits, bytes, and words, Numeric data representation and number bases, Fixed- and floating-point systems, Signed and twos-complement representations, Representation of non-numeric data (character codes, graphical data), Representation of records and arrays
- Basic organization of the von Neumann machine, Control unit; Instruction fetch, decode, and execution, Instruction sets and types (data manipulation, control, I/O), Registers; Register transfer notation
- Assembly/machine language programming, Instruction formats, Addressing modes
- Assembly/machine language programming
- Assembly/machine language programming, Subroutine call and return mechanisms
- I/O and interrupts, I/O fundamentals (handshaking, buffering, programmed I/O, interrupt-driven I/O), Interrupt structures (vectored and prioritized, interrupt acknowledgment)
- External storage, physical organization, and drives, Buses: bus protocols, arbitration, direct-memory access (DMA)
- Midterm exam
- Control unit; Instruction fetch, decode, and execution, Instruction sets and types (data manipulation, control, I/O), Instruction formats, Addressing modes
- Assembly/machine language programming
- I/O and interrupts, I/O fundamentals (handshaking, buffering, programmed I/O, interrupt-driven I/O), Interrupt structures (vectored and prioritized, interrupt acknowledgment)
- Main memory organization and operations, Buses: bus protocols, arbitration, direct-memory access (DMA)
- Implementation of simple datapaths (including instruction pipelining, hazard detection, and resolution)
- Storage systems and their technology, Memory hierarchy (importance of temporal and spatial locality), Main memory organization and operations, Latency, cycle time, bandwidth, and interleaving
- Final exam
Literature
Mario Kovač (.), Arhitektura računala (knjiga),
Mario Kovač, Danko Basch (.), Rukopisi s predavanja,
Danko Basch, Martin Žagar, Branko Mihaljević, Marin Orlić, Josip Knezović, Ivana Bosnić, Daniel Hofman, Mario Kovač (.), Zbirka programskih zadataka za procesor FRISC,
Martin Žagar, Josip Knezović, Ivana Bosnić, Mario Kovač (.), Zbirka programskih zadataka za procesor ARM 7,
General
ID 209646
Winter semester
6 ECTS
L0 English Level
L1 e-Learning
60 Lectures
0 Seminar
0 Exercises
18 Laboratory exercises
0 Project laboratory
0 Physical education excercises
Grading System
90 Excellent
80 Very Good
65 Good
50 Sufficient