System Level Integration

Course Description

System level integration for System on chip. Executable functional specifications and virtual prototyping. Hardware and software modeling and verification in control, communication and multimedia systems. System architecture definition and IP block selection. Methodology of integrating pre-defined IP blocks in a hierarchical process with timing constraints. Designing semiconductor intellectual properties. IP qualification. IP authoring. Platform based design.

General Competencies

Students learn design methodology for system level integration, design reuse, intellectual properties blocks integration and authoring. They learn how to partition the system and arrive from specification to transistor level description. They learn how to specify, analyze and realize system in silicon from pre-defined blocks of intellectual property. The course provides students with the knowledge, understanding and skills needed to be of immediate value to employers.

Learning Outcomes

Forms of Teaching

Week by Week Schedule

Study Programmes

University graduate
Computer Engineering (profile)
Specialization Course (1. semester) (3. semester)

Literature

(.), Reuse Methodology Manual for System-on-A-Chip Design Keating, Bricaud 2004,
(.), Reuse Techniques for LSI design R. Seepold and A. Kunzman Kluwer Academic Publishers 1999,
(.), The Electronic Design Automation Handbook Dirk Jansen et al. Kluwer Academic Publishing 2003,

General

ID 34529
  Winter semester
4 ECTS
L0 English Level
L1 e-Learning
30 Lectures
0 Exercises
0 Laboratory exercises
0 Project laboratory

Grading System

Excellent
Very Good
Good
Acceptable