EPAC1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful. One of the partners that are working on this project is the HPC Architecture and Application Research Center (Faculty of Electrical Engineering and Computing).
The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb.
More about the test chip and EPI project goals here: https://www.vidi.hr/Non-Tech/Hrvatska/Hrvatski-FER-radi-europski-procesor.
