Tools for Digital Design
Knowledge in design of complex digital systems by using hardware description languages.
- describe system level design
- describe the architecture of FPGA circuits
- employ VHDL
- develop a digital system using VHDL
- categorize the requirements set on a digital system
- assemble digital subsystems into a complete system
- analyze the data obtained by testing of digital systems
Forms of Teaching
2 hours once every weekExams
midterm exam and final examLaboratory Work
4 times in semesterConsultations
|Type||Threshold||Percent of Grade||Comment:||Percent of Grade|
|Laboratory Exercises||0 %||15 %||0 %||15 %|
|Mid Term Exam: Written||0 %||35 %||0 %|
|Final Exam: Written||0 %||50 %|
|Exam: Written||0 %||85 %|
The pass is acquired if minimum 50% is gained of the available score on the written part of the exam.
Week by Week Schedule
- Modeling of digital systems. Development of hardware description languages (HDL). Digital system design using HDL.
- Elements of VHDL. Objects and types. Scalar types. Subtypes. Types conversion.
- Attributes of scalar types. Attributes of signals. VHDL model. Entity declaration. Architecture. Process. Sequential statements.
- Delay element. Assertion statement. Composite types. Components.
- Multisource drive. Design of digital system. Behavioral model, test bench, RTL model.
- Subprograms. Packages and libraries. Components and configurations.
- Figure of merit of digital system complexity. Phases of design of digital system. Implementation technologies. Field programmable gate arrays (FPGAs).
- Midterm exam.
- Basic element of synchronous design and its implementation. Arithmetic operations and their implementation. Implementation of basic functions on FPGAs.
- Modeling for specific target platform. Modeling of memories, multipliers and their implementation on FPGAs. Modeling of input-output blocks.
- Modeling of finite state machines and their implementation on FPGAs.
- Simulators. Integration and testing of digital system. Development of generic components.
- Files in VHDL. Use of files in synthesis and verification.
- User attributes. Specification of pinout and timing requirements. Automatic generation of VHDL models.
- Final exam.