Digital System Design

Course Description

This course deals with principles of complex digital system design by means of development environments, which allow design automation based on hardware description languages. The different modelling levels and approaches to digital system design are considered based on complex digital components.

General Competencies

The course enables the students to understand basic concepts of complex digital system design based on development environments, which allow design automation by means of hardware description languages.

Learning Outcomes

  1. define concepts (VHDL, ASIC, design techniques, levels of abstraction, bus systems) of complex digital systems.
  2. explain and distinguish porocedures and methods in the field of complex digital system design
  3. apply design methods for new applications
  4. analyze and breakdown a complex digital system
  5. design and develop a VHDL model of a system
  6. design and develop a complex digital system based on ASIC
  7. evaluate performance of a system based on VHDL/ASIC

Forms of Teaching


Classes are held in two phases - each 7 weeks. Classes are conducted over 15 weeks with a weekly load of three hours. After each phase, ie, in the 7th week of lectures and 15th week of lectures exames are held.


Knowledge checking is done by written examination twice in a semester.


Consultations are planned for 2 hours per week.


Groups of 4 to 5 students receive project tasks. The group solves problem, implements the program solution (VHDL) and hardware solution (Spartan 3 - FPGA).

Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Comment: Percent of Grade
Seminar/Project 50 % 30 % 0 % 30 %
Mid Term Exam: Written 50 % 30 % 50 %
Final Exam: Written 50 % 40 %
Exam: Written 50 % 70 %

Week by Week Schedule

  1. Product development process (complex digital system)- phases and levels. Design objectives.
  2. Design automation. Design metrics. Models and art of modeling. Modularity of software and hardware.
  3. Hardware description languages (HDL). Short overview of HDL development. Languages for behavioral description. Languages for describing flow of data. Languages for describing netlists.
  4. Building components of complex digital systems. Basic programable digital components. Application-Specific Integrated Circuits (ASIC). Taxonomy of ASIC.
  5. Implementation description: from idea to target FPGA. Multilevel system design. HDL: VHDL and Verilog. Levels of abstraction. VHDL design units.
  6. Design methodology: Top-down and Bottom-up.
  7. Midterm exam
  8. Top-Down design with VHDL - An example.(Part I.)
  9. Top-Down design with VHDL - An example. (Part II.)
  10. Bus systems. Analysis of asynchronous and synchronous bus protocols.
  11. Types of bus cycles. Bus arbitration (centralized and distributed). Bus standards. Case study.
  12. SCSI bus standard.
  13. PCI bus
  14. VME - bus standard
  15. Final exam.

Study Programmes

University graduate
Computer Engineering (profile)
Theoretical Course (2. semester)


Z. Navabi (1997.), VHDL-Analysis and Modeling of Digital Systems, McGraw-Hill Professional
M.J. S. Smith (1997.), Application-Specific Integrated Circuits, Addison-Wesley
Z. Salcic, A. Smailagic (2000.), Digital System Design and Prototyping, Kluwer
P. J. Ashenden, J. Lewis (2008.), The Designer’s Guide to VHDL, Morgan Kaufmann
Pong P. Chu (2008.), FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience

Grading System

ID 34508
  Summer semester
L1 English Level
L1 e-Learning
45 Lecturers
0 Exercises
0 Laboratory exercises


89 Excellent
74 Very Good
61 Good
50 Acceptable