Digital System Design
The course enables the students to understand basic concepts of complex digital system design based on development environments, which allow design automation by means of hardware description languages.
- define concepts (VHDL, ASIC, design techniques, levels of abstraction, bus systems) of complex digital systems.
- explain and distinguish porocedures and methods in the field of complex digital system design
- apply design methods for new applications
- analyze and breakdown a complex digital system
- design and develop a VHDL model of a system
- design and develop a complex digital system based on ASIC
- evaluate performance of a system based on VHDL/ASIC
Forms of Teaching
Classes are held in two phases - each 7 weeks. Classes are conducted over 15 weeks with a weekly load of three hours. After each phase, ie, in the 7th week of lectures and 15th week of lectures exames are held.Exams
Knowledge checking is done by written examination twice in a semester.Consultations
Consultations are planned for 2 hours per week.Seminars
Groups of 4 to 5 students receive project tasks. The group solves problem, implements the program solution (VHDL) and hardware solution (Spartan 3 - FPGA).
|Type||Threshold||Percent of Grade||Comment:||Percent of Grade|
|Seminar/Project||50 %||30 %||0 %||30 %|
|Mid Term Exam: Written||50 %||30 %||50 %|
|Final Exam: Written||50 %||40 %|
|Exam: Written||50 %||70 %|
Week by Week Schedule
- Product development process (complex digital system)- phases and levels. Design objectives.
- Design automation. Design metrics. Models and art of modeling. Modularity of software and hardware.
- Hardware description languages (HDL). Short overview of HDL development. Languages for behavioral description. Languages for describing flow of data. Languages for describing netlists.
- Building components of complex digital systems. Basic programable digital components. Application-Specific Integrated Circuits (ASIC). Taxonomy of ASIC.
- Implementation description: from idea to target FPGA. Multilevel system design. HDL: VHDL and Verilog. Levels of abstraction. VHDL design units.
- Design methodology: Top-down and Bottom-up.
- Midterm exam
- Top-Down design with VHDL - An example.(Part I.)
- Top-Down design with VHDL - An example. (Part II.)
- Bus systems. Analysis of asynchronous and synchronous bus protocols.
- Types of bus cycles. Bus arbitration (centralized and distributed). Bus standards. Case study.
- SCSI bus standard.
- PCI bus
- VME - bus standard
- Final exam.