Tools for Digital Design

Learning Outcomes

  1. describe system level design
  2. describe the architecture of CPLD, FPGA andSoC circuits
  3. employ a hardware description language (HDL)
  4. develop a digital system using hardware description language
  5. categorize the requirements set on a digital system
  6. assemble digital subsystems into a complete system
  7. analyze the data obtained by testing of digital systems

Forms of Teaching

Lectures

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Independent assignments

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Laboratory

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Grading Method

     
Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 0 % 20 % 0 % 20 %
Mid Term Exam: Written 0 % 35 % 0 %
Final Exam: Written 0 % 45 %
Exam: Written 50 % 80 %
Comment:

The pass is acquired if minimum 50% is gained of the available score on the written part of the exam.

Week by Week Schedule

  1. Principles; System level design.
  2. Language elements.
  3. Behavioral model; Language elements.
  4. Register transfer level (RTL) model; Language elements.
  5. Language elements; Practical examples in VHDL and Verilog.
  6. Code structure and organization; Practical examples in VHDL and Verilog.
  7. Practical examples in VHDL and Verilog; Test bench; Functional simulation.
  8. Midterm exam.
  9. Measures of complexity; Implementation platforms ASICS, FPGA, CPLD.
  10. Computer-aided design tools that process hardware and architectural representations; Implementation platforms ASICS, FPGA, CPLD.
  11. Computer-aided design tools that process hardware and architectural representations; Generic and vendor agnostic design.
  12. Practical examples in VHDL and Verilog; Timing simulation.
  13. Computer-aided design tools that process hardware and architectural representations; Case study.
  14. Case study; Formal verification of digital systems.
  15. Final exam.

Study Programmes

University undergraduate
Computing (study)
Elective Courses (5. semester)
Electrical Engineering and Information Technology (study)
Elective Courses (5. semester)

Literature

M. Vučić, G. Molnar (2018.), Alati za razvoj digitalnih sustava - Materijali za predavanja I, FER-ZESOI
M. Vučić, G. Molnar (2009.), Alati za razvoj digitalnih sustava - Materijali za predavanja II, FER-ZESOI
M. Vučić, G. Molnar (2009.), Alati za razvoj digitalnih sustava - Materijali za predavanja III, FER-ZESOI
M. Butorac, G. Molnar, M. Vučić (2015.), Alati za razvoj digitalnih sustava - Upute za praktični rad I,
G. Molnar, M. Vučić (2009.), Alati za razvoj digitalnih sustava - Upute za praktični rad II, FER-ZESOI
P. J. Ashenden (2008.), The Designer's Guide to VHDL, Morgan Kaufmann Publishers
P. J. Ashenden (2008.), Digital Design - An Embedded Systems Approach Using VerilogThe Designer's Guide to VHDL, Morgan Kaufmann Publishers
L. H. Crockett, R. A. Elliot, M. A. Enderwitz, R. W. Stewart (2014.), The Zynq Book - Embedded Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC, Strathclyde Academic Media

General

ID 183417
  Winter semester
5 ECTS
L0 English Level
L1 e-Learning
30 Lectures
0 Exercises
12 Laboratory exercises
0 Project laboratory

Grading System

88 Excellent
75 Very Good
62 Good
50 Acceptable