Tools for Digital Design

Course Description

Trends in development of complex digital systems. Digital design based on hardware description languages (HDL). Hierarchical design. Element and data flow modeling. HDL model; entity and architecture. System level design; behavioral model, test bench, register transfer level (RTL) model. Interface to the environment. Source code organization. Practical aspects of design using HDL. Design of combinational and sequential functions. HDL design of state machines. Design of digital signal processing systems. Implementation. Functional and timing simulation of gate level model. New generations of programmable logic devices (CPLD) and arrays (FPGA). State of the art in technology of programmable devices, their configuration and verification. Intellectual property. Development systems and tools. Design example.

General Competencies

Knowledge in design of complex digital systems by using hardware description languages.

Learning Outcomes

  1. describe system level design
  2. describe the architecture of FPGA circuits
  3. employ VHDL
  4. develop a digital system using VHDL
  5. categorize the requirements set on a digital system
  6. assemble digital subsystems into a complete system
  7. analyze the data obtained by testing of digital systems

Forms of Teaching


2 hours once every week


midterm exam and final exam

Laboratory Work

3 times in semester



Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 0 % 15 % 0 % 15 %
Mid Term Exam: Written 0 % 35 % 0 %
Final Exam: Written 0 % 50 %
Exam: Written 50 % 85 %

The pass is acquired if minimum 50% is gained of the available score on the written part of the exam.

Week by Week Schedule

  1. Modeling of digital systems. Development of hardware description languages (HDL). Digital system design using HDL.
  2. Elements of VHDL. Objects and types. Scalar types. Subtypes. Types conversion.
  3. Attributes of scalar types. Attributes of signals. VHDL model. Entity declaration. Architecture. Process. Sequential statements.
  4. Delay element. Assertion statement. Composite types. Components.
  5. Multisource drive. Design of digital system. Behavioral model, test bench, RTL model.
  6. Subprograms. Packages and libraries. Components and configurations.
  7. Figure of merit of digital system complexity. Phases of design of digital system. Implementation technologies. Field programmable gate arrays (FPGAs).
  8. Midterm exam.
  9. Basic element of synchronous design and its implementation. Arithmetic operations and their implementation. Implementation of basic functions on FPGAs.
  10. Modeling for specific target platform. Modeling of memories, multipliers and their implementation on FPGAs. Modeling of input-output blocks.
  11. Modeling of finite state machines and their implementation on FPGAs.
  12. Simulators. Integration and testing of digital system. Development of generic components.
  13. Files in VHDL. Use of files in synthesis and verification.
  14. User attributes. Specification of pinout and timing requirements. Automatic generation of VHDL models.
  15. Final exam.

Study Programmes

University graduate
Computer Engineering (profile)
Specialization Course (1. semester) (3. semester)
Electronic and Computer Engineering (profile)
Specialization Course (3. semester)
Electronics (profile)
Specialization Course (3. semester)


Mladen Vučić, Goran Molnar (2003.), Alati za razvoj digitalnih sustava - Materijali za predavanja I, II i III, FER
Marko Butorac, Goran Molnar, Mladen Vučić (2009.), Alati za razvoj digitalnih sustava - Upute za praktični rad I, FER
Peter J. Ashenden (2008.), The Designers Guide to VHDL, Morgan Kaufmann
Pong P. Chu (2008.), FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, John Wiley and Sons

Laboratory exercises

For students


ID 86445
  Winter semester
L0 English Level
L1 e-Learning
30 Lectures
6 Laboratory exercises

Grading System

88 Excellent
75 Very Good
62 Good
50 Acceptable