System on Chip Platform Programming

Data is displayed for academic year: 2023./2024.

Lecturers

Prof.
Hrvoje Mlinarić
Assoc. Prof.
Vlado Sruk

Course Description

This course introduces students with the concepts, issues, and process of designing highly integrated SoCs following systematic hardware/software co-design. Students gains knowledge of system partitioning and design based on specifications using intellectual property blocks, the methodology of integrating predefined IP blocks into a hierarchical process with time constraints. Explain system architecture, IP block selection, IP authoring, Platform based design and application of SystemC.

Study Programmes

University graduate
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[FER3-HR] Electronic and Computer Engineering - profile
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[FER3-HR] Electronics - profile
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[FER3-HR] Network Science - profile
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[FER3-HR] Software Engineering and Information Systems - profile
Elective Courses (1. semester) (3. semester)

Learning Outcomes

  1. Analyze the functional and nonfunctional performance of the system early in the design process.
  2. Evaluate algorithms, and architectures to optimize the system based on requirements and implementation constraints.
  3. Apply hardware, software, and interface synthesis.
  4. Demonstrate examples of applications and systems developed using a co-design approach

Forms of Teaching

Lectures

Lectures are held during 13 weeks in the semester, with 3 hours of lectures per week.

Independent assignments

Laboratory exercises are conducted in the form of project during the whole semester.

Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Seminar/Project 50 % 30 % 0 % 25 %
Mid Term Exam: Written 0 % 30 % 0 %
Final Exam: Written 50 % 40 %
Exam: Written 50 % 75 %

Week by Week Schedule

  1. Requirements analysis and identification of optimal HW/SW platform
  2. Requirements analysis and identification of optimal HW/SW platform, Design methodologies for HW/SW co-design
  3. Partitioning and integration of HW/SW solution, Design methodologies for HW/SW co-design
  4. Partitioning and integration of HW/SW solution
  5. Partitioning and integration of HW/SW solution, Architecture generation - program translation to architecture
  6. High level programming support for heterogeneous embedded systems (DSL- Domain Specific Language support: streaming, signal processing, etc;)
  7. High level programming support for heterogeneous embedded systems (DSL- Domain Specific Language support: streaming, signal processing, etc;)
  8. Midterm exam
  9. Programming models for HW/SW codesign, heterogeneous systems, accelerators (GPU, coprocessors, programmable logic)
  10. Programming models for HW/SW codesign, heterogeneous systems, accelerators (GPU, coprocessors, programmable logic)
  11. FPGA platform development tools, system-level programming
  12. FPGA platform development tools, system-level programming, HW/SW partitioning for FPGA platform development
  13. HW/SW partitioning for FPGA platform development
  14. High-level memory management for embedded systems runtimes (garbage collection, memory allocation, flash wear leveling)
  15. Final exam

Literature

Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, Gunar Schirner (2009.), Embedded System Design, Springer Science & Business Media
Peter Marwedel (2021.), Embedded System Design, Springer Nature
David C. Black, Jack Donovan, Bill Bunton, Anna Keist (2014.), SystemC: From the Ground Up, Second Edition, Springer
Sanjay Churiwala (2016.), Designing with Xilinx® FPGAs, Springer

For students

General

ID 222683
  Winter semester
5 ECTS
L1 English Level
L2 e-Learning
45 Lectures
0 Seminar
0 Exercises
0 Laboratory exercises
0 Project laboratory

Grading System

86 Excellent
72 Very Good
60 Good
50 Sufficient

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