Digital Logic

Learning Outcomes

  1. choose the appropriate level of standard combinational and sequential components to design simple digital circuits
  2. design simple combinational and sequential digital circuits
  3. analyze simple combinational and sequential digital circuits
  4. apply Boolean algebra as a formalism for describing of combinational and sequential digital circuits
  5. apply the VHDL hardware description language in modeling and simulation of simple combinational and sequential digital circuits
  6. identify and classify standard and programmable combinational and sequential digital circuits
  7. recognize the limitations represented by dynamic and electrical properties of digital circuits and their interconnections

Forms of Teaching

Lectures

Lectures will be given in two hours blocks twice a week.

Exercises

Excercises will be held one hour per week.

Laboratory

Laboratory exercises will be held in two hours blocks.

Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 50 % 15 % 50 % 15 %
Homeworks 0 % 10 % 0 % 0 %
Quizzes 0 % 5 % 0 % 0 %
Class participation 0 % 10 % 0 % 0 %
Mid Term Exam: Written 0 % 30 % 0 %
Final Exam: Written 40 % 40 %
Exam: Written 50 % 85 %
Comment:

Short evaluations will be in principle performed by assigning short tests during the lectures.

Week by Week Schedule

  1. Analog values and their digital representation, Binary system, binary arithmetic, basic operations: addition, subtraction, and multiplication
  2. Binary codes and coding; Error detecting and error correcting codes, Number systems and codes
  3. Basic logic circuits: AND, OR, NOT, NAND, NOR, and EX-OR
  4. Minimization of Boolean functions: algebraic and Karnaugh maps; Minimization requirements and limitations; Incompletely specified functions; Delay and hazard
  5. Implementation of Boolean functions; Integrated digital circuits; Electrical characteristics
  6. Standard combinational modules: decoders, demultiplexors, multiplexors, ROMs, priority encoders, and comparators, VHDL models of combinational modules, Standard combinational module implementation of Boolean functions
  7. Arithmetic circuits: adders, carry look-ahead generators, subtractors, multipliers, and shifters
  8. Midterm exam
  9. PLDs and FPGAs, Programmable module implementation of Boolean functions
  10. Basic latch, Flip-flop and flip-flop types, Triggering and dynamic parameters
  11. Sequential circuits; Finite state machines; Moore and Mealy automata; State diagram and table, Design of synchronous sequential circuits; State minimization; State coding, Analysis of synchronous sequential circuits
  12. Standard sequential modules: registers, shift registers, and counters (ripple and synchronous)
  13. D/A conversion, A/D conversion
  14. Characteristic parameters of memories, Static and dynamic memories, Memory modules organization
  15. Final exam

Study Programmes

University undergraduate
Electrical Engineering and Information Technology and Computing (study)
(1. semester)

Literature

Uroš Peruško, Vlado Glavinić (2005.), Digitalni sustavi, Školska knjiga
Marko Čupić (2006.), Digitalna elektronika i digitalna logika : zbirka riješenih zadataka, Kigen
Stephen D. Brown, Zvonko G. Vranesic (2009.), Fundamentals of Digital Logic with VHDL Design, McGraw-Hill

Lecturers

Exercises

Laboratory exercises

Grading System

ID 183360
  Winter semester
6 ECTS
L3 English Level
L1 e-Learning
60 Lectures
15 Exercises
15 Laboratory exercises
0 Project laboratory

General

88 Excellent
75 Very Good
62 Good
50 Acceptable