Design and verification of digital logic using System Verilog and UVM

Data is displayed for academic year: 2023./2024.

Study Programmes

University undergraduate
Skills (3. semester) (5. semester)
Skills (3. semester) (5. semester)
University graduate
[FER3-HR] Computing - study
Skills (1. semester) (3. semester)
[FER3-HR] Electrical Engineering and Information Technology - study
Skills (1. semester) (3. semester)
[FER3-HR] Information and Communication Technology - study
Skills (1. semester) (3. semester)

For students

General

ID 268532
  Winter semester
3 ECTS
26 Lectures
0 Seminar
0 Exercises
16 Laboratory exercises
0 Project laboratory
0 Physical education excercises