Computer Architecture 2

Learning Outcomes

  1. distinguish the roles of major components of a computer including CPU, memory, buses and I/O devices.
  2. predict activity on the memory bus of a simple procesor, as a consequence of execution of short machine code snippets
  3. demonstrate the implementation of simple instructions at the logic level
  4. summarize design principles of instruction set architectures RISC and x86
  5. solve small-scale problems by complementing C with assembly
  6. summarize the organization of superscalar processors with dynamic pipeline scheduling
  7. illustrate stages of physical address generation in presence of caches and virtual memory
  8. explain the implementation of coarse-grained parallelism on multi-core and multi-processor computers

Forms of Teaching

Lectures

The course includes three hours of lectures per week.

Laboratory

The course includes two laboratory exercises. http://www.zemris.fer.hr/~ssegvic/ar2/index_en.html

Grading Method

     
Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 40 % 15 % 40 % 0 %
Mid Term Exam: Written 0 % 40 % 0 %
Final Exam: Written 0 % 45 %
Exam: Written 50 % 80 %
Exam: Oral 80 %

Week by Week Schedule

  1. Control unit (hardwired realization vs; microprogrammed realization).
  2. Control unit (hardwired realization vs; microprogrammed realization).
  3. Control unit (hardwired realization vs; microprogrammed realization).
  4. Control unit (hardwired realization vs; microprogrammed realization).
  5. Heap vs; static vs; stack vs; code segments.
  6. Cache memories (address mapping, block size, replacement and store policy).
  7. Cache memories (address mapping, block size, replacement and store policy).
  8. Midterm exam.
  9. Instruction pipelining.
  10. Introduction to instruction-level parallelism (ILP).
  11. Superscalar architecture.
  12. Virtual memory (page table, TLB).
  13. Shared memory multiprocessors/multicore organization; Introduction to SIMD vs; MIMD and the Flynn Taxonomy; Multicore and manycore systems.
  14. Shared multiprocessor memory systems and memory consistency; Vector processors and GPUs; Hardware support for multithreading.
  15. Final exam.

Study Programmes

University undergraduate
Computer Engineering (module)
(5. semester)
Computer Science (module)
Specialization courses (5. semester)
Computing (study)
Elective Courses (5. semester)
Electrical Engineering and Information Technology (study)
Elective Courses (5. semester)
Information Processing (module)
Specialization courses (5. semester)
Telecommunication and Informatics (module)
Specialization courses (5. semester)

Literature

(.), S. RIbarić. Građa računala, Arhitektura i organizacija računarskih sustava,
(.), D. A. Patterson J. L. Hennessy. Computer Organization Design,

General

ID 183428
  Winter semester
5 ECTS
L3 English Level
L1 e-Learning
60 Lectures
0 Exercises
8 Laboratory exercises
0 Project laboratory

Grading System

89 Excellent
76 Very Good
63 Good
50 Acceptable