Computer Architecture 2

Data is displayed for academic year: 2023./2024.

Lecturers

Assoc. Prof.
Tomislav Hrkać
Prof.
Slobodan Ribarić
Prof.
Siniša Šegvić

Course Description

This course studies architectural components of computer systems: processor, memory, buses, and IO devices. The course considers design approaches which allow us to achieve the desired performance and price of computer system. The main fields of interest are i) specificities of general purpose computer architecture, ii) organizational details of the architectural components which affect the software performance, and iii) exploiting the parallelism at the levels of instructions, vector instructions and threads.

Study Programmes

University undergraduate
[FER3-EN] Computing - study
Elective Courses (5. semester)
[FER3-EN] Electrical Engineering and Information Technology - study
Elective Courses (5. semester)

Learning Outcomes

  1. distinguish the roles of major components of a computer including CPU, memory, buses and I/O devices.
  2. predict activity on the memory bus of a simple procesor, as a consequence of execution of short machine code snippets
  3. demonstrate the implementation of simple instructions at the logic level
  4. summarize design principles of instruction set architectures RISC and x86
  5. solve small-scale problems by complementing C with assembly
  6. summarize the organization of superscalar processors with dynamic pipeline scheduling
  7. illustrate stages of physical address generation in presence of caches and virtual memory
  8. explain the implementation of coarse-grained parallelism on multi-core and multi-processor computers

Forms of Teaching

Lectures

The course does not include lectures in English.

Laboratory

The course includes two laboratory exercises. http://www.zemris.fer.hr/~ssegvic/ar2/index_en.html

Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 50 % 20 % 50 % 0 %
Mid Term Exam: Written 0 % 40 % 0 %
Final Exam: Written 0 % 40 %
Exam: Written 50 % 80 %
Exam: Oral 80 %

Week by Week Schedule

  1. Control unit (hardwired realization vs; microprogrammed realization)
  2. Control unit (hardwired realization vs; microprogrammed realization)
  3. Control unit (hardwired realization vs; microprogrammed realization)
  4. Control unit (hardwired realization vs; microprogrammed realization)
  5. Adress space layout: heap, stack, static data, code segment.
  6. Cache memories (address mapping, block size, replacement and store policy)
  7. Cache memories (address mapping, block size, replacement and store policy)
  8. Midterm exam
  9. Instruction pipelining
  10. Introduction to instruction-level parallelism (ILP)
  11. Superscalar architecture
  12. Virtual memory (page table, TLB)
  13. Comparison of CPUs and GPUs. Hardware organization of GPUs. Introduction to OpenCL.
  14. Shared multiprocessor memory systems and memory consistency, Vector processors and GPUs, Hardware support for multithreading
  15. Final exam

Literature

(.), S. RIbarić. Građa računala, Arhitektura i organizacija računarskih sustava,
(.), D. A. Patterson J. L. Hennessy. Computer Organization Design,

For students

General

ID 210655
  Winter semester
5 ECTS
L1 English Level
L1 e-Learning
60 Lectures
0 Seminar
0 Exercises
8 Laboratory exercises
0 Project laboratory
0 Physical education excercises

Grading System

89 Excellent
76 Very Good
63 Good
50 Sufficient

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