Computer Architecture 2

Course Description

This course studies architectural components of computer systems: processor, memory, buses, and IO devices. The course considers design approaches which allow us to achieve the desired computer system properties: performance, price, power consumption, reliability. The main fields of interest are i) specificities of general purpose computer architecture, ii) organizational details of the architectural components which affect the software performance, and iii) exploiting the parallelism at the levels of instructions, vector instructions and threads.

General Competencies

The students are trained for solving problems related to design, configuration and utilization of general purpose computers. Lectures and laboratory exercises stimulate associating architectural and organizational concepts with recent case studies. In particular, the students are acquainted with detailed organization of a simplified processor, performance metrics, instruction set architectures, dynamic pipeline scheduling, memory hierarchy, multi-processor and multi-core systems, and consequences which affect software design.

Learning Outcomes

  1. distinguish the roles of major components of a computer including CPU, memory, buses and I/O devices.
  2. predict activity on the memory bus of a simple procesor, as a consequence of execution of short machine code snippets
  3. demonstrate the implementation of simple instructions at the logic level
  4. summarize design principles of instruction set architectures RISC and x86
  5. solve small-scale problems by complementing C with assembly
  6. summarize the organization of superscalar processors with dynamic pipeline scheduling
  7. illustrate stages of physical address generation in presence of caches and virtual memory
  8. explain the implementation of coarse-grained parallelism on multi-core and multi-processor computers

Forms of Teaching


The course includes three hours of lectures per week.


The knowledge tests include the midterm exam (40%), the final exam (45%), two short tests in class and three tests in the laboratory (15%).

Laboratory Work

The course includes two laboratory exercises.


Consultations are held once a week within a time slot of two hours.


The students may earn additional credits by completing a technical seminar. The subject of the seminar must be registered before the mid-term exam.

Grading Method

Continuous Assessment Exam
Type Threshold Percent of Grade Threshold Percent of Grade
Laboratory Exercises 40 % 15 % 40 % 0 %
Mid Term Exam: Written 0 % 40 % 0 %
Final Exam: Written 0 % 45 %
Exam: Written 50 % 80 %
Exam: Oral 20 %

Week by Week Schedule

  1. Introduction. Trends in VLSI technology, computer architecture, and processor performance. Roles of major components in the Von Neumann's computer model including CPU, memory, buses and I/O devices. Implementing a shared bus with three-state buffers. Problem solving exercises.
  2. Simplified model of the processor organization. Tracking the memory activity during the execution of short machine code snippets. Problem solving exercises.
  3. Hardwired control in a 8-instruction processor model. Implementation of simple instructions at the gate level. Components of control unit: sequence counter, decoder, logic array, clock generator. Problem solving exercises.
  4. Implementation of control in the model of the microprogrammable processor: microprogrammable processor model, organization and structure of the microprogrammable control unit, microinstruction formats. Problem solving exercises.
  5. Hardware/software interface: stacks, exceptions, creation of executable files, memory layout of a typical process. Problem solving exercises.
  6. Computer architecture classifications with respect to parallelism (Flynn), control flow (instruction, data), and instruction sets (CISC, RISC, VLIW). Computer performance: introduction of the parameter CPI, SPEC benchmark collections. Problem solving exercises.
  7. Instruction set architectures RISC and x86. Data path of a modern RISC processor. Problem solving exercises.
  8. Midterm exam.
  9. The concept of pipelined data processing. Pipeline hazards: structural, data, and control. Organization of a pipelined RISC processor.
  10. Aggresive exploitation of instruction-level parallelism. Superscalar organization. Dynamic scheduling. Register renaming. Branch prediction. Case studies.
  11. Memory hierarchy. Approaches for improving the bandwidth of the main storage. Cache organization: direct-mapped, fully associative and set-associative. Replacement algorithms. Cache coherency. Case studies. Problem solving exercises.
  12. Virtual memory system. Physical and logical address spaces. Address mapping by paging and segmentation. TLB-s and multi level page tables. Replacement policies. Case studies. Problem solving exercises.
  13. Forms and levels of parallelism. Parallel architectures. Multiprocessor SIMD computers. Vector processors.
  14. Multiprocessor MIMD computers. Multiprocessor cache coherency. Synchronization of processes and threads. Multicore processors. Graphic processors.
  15. Final exam

Study Programmes

University undergraduate
Computer Engineering (module)
(5. semester)
Computer Science (module)
Specialization courses (5. semester)
Information Processing (module)
Specialization courses (5. semester)
Telecommunication and Informatics (module)
Specialization courses (5. semester)


S. Ribarić (2011.), Građa računala, Arhitektura i organizacija računarskih sustava, Algebra, Zagreb
S. Ribarić (1996.), Arhitektura računala RISC i CISC, Školska knjiga
D. A. Patterson J. L. Hennessy (2008.), Computer Organization & Design, Morgan Kaufmann
J. L. Hennessy, D. A. Patterson (2006.), Computer Architecture, A Quantitative Approach, Morgan Kaufmann
Slobodan Ribarić (2017.), Zbirka riješenih zadataka iz Građe računala, arhitekture i organizacije računarskih sustava, Merkur A.B.D

Laboratory exercises


ID 34277
  Winter semester
L1 English Level
L1 e-Learning

Grading System

89 Excellent
76 Very Good
63 Good
50 Acceptable