Computer Architecture 2
Data is displayed for academic year: 2023./2024.
Course Description
This course studies architectural components of computer systems: processor, memory, buses, and IO devices. The course considers design approaches which allow us to achieve the desired performance and price of computer system. The main fields of interest are i) specificities of general purpose computer architecture, ii) organizational details of the architectural components which affect the software performance, and iii) exploiting the parallelism at the levels of instructions, vector instructions and threads.
Study Programmes
University undergraduate
[FER3-EN] Computing - study
Elective Courses
(5. semester)
[FER3-EN] Electrical Engineering and Information Technology - study
Elective Courses
(5. semester)
Learning Outcomes
- distinguish the roles of major components of a computer including CPU, memory, buses and I/O devices.
- predict activity on the memory bus of a simple procesor, as a consequence of execution of short machine code snippets
- demonstrate the implementation of simple instructions at the logic level
- summarize design principles of instruction set architectures RISC and x86
- solve small-scale problems by complementing C with assembly
- summarize the organization of superscalar processors with dynamic pipeline scheduling
- illustrate stages of physical address generation in presence of caches and virtual memory
- explain the implementation of coarse-grained parallelism on multi-core and multi-processor computers
Forms of Teaching
Lectures
The course does not include lectures in English.
LaboratoryThe course includes two laboratory exercises. http://www.zemris.fer.hr/~ssegvic/ar2/index_en.html
Grading Method
Continuous Assessment | Exam | |||||
---|---|---|---|---|---|---|
Type | Threshold | Percent of Grade | Threshold | Percent of Grade | ||
Laboratory Exercises | 50 % | 20 % | 50 % | 0 % | ||
Mid Term Exam: Written | 0 % | 40 % | 0 % | |||
Final Exam: Written | 0 % | 40 % | ||||
Exam: Written | 50 % | 80 % | ||||
Exam: Oral | 80 % |
Week by Week Schedule
- Control unit (hardwired realization vs; microprogrammed realization)
- Control unit (hardwired realization vs; microprogrammed realization)
- Control unit (hardwired realization vs; microprogrammed realization)
- Control unit (hardwired realization vs; microprogrammed realization)
- Adress space layout: heap, stack, static data, code segment.
- Cache memories (address mapping, block size, replacement and store policy)
- Cache memories (address mapping, block size, replacement and store policy)
- Midterm exam
- Instruction pipelining
- Introduction to instruction-level parallelism (ILP)
- Superscalar architecture
- Virtual memory (page table, TLB)
- Comparison of CPUs and GPUs. Hardware organization of GPUs. Introduction to OpenCL.
- Shared multiprocessor memory systems and memory consistency, Vector processors and GPUs, Hardware support for multithreading
- Final exam
Literature
(.), S. RIbarić. Građa računala, Arhitektura i organizacija računarskih sustava,
(.), D. A. Patterson J. L. Hennessy. Computer Organization Design,
For students
General
ID 210655
Winter semester
5 ECTS
L1 English Level
L1 e-Learning
60 Lectures
0 Seminar
0 Exercises
8 Laboratory exercises
0 Project laboratory
0 Physical education excercises
Grading System
89 Excellent
76 Very Good
63 Good
50 Sufficient